Field of the Invention
The invention lies in the semiconductor field. Specifically, the present invention relates to a memory cell configuration with a multiplicity of preferably ferroelectric memory cells provided in a semiconductor substrate (ferroelectric memory (FeRAM) or nonvolatile random-access memory (NVRAM)) and to a corresponding fabrication method.
Although applicable to memories made of any desired base material, the present invention and also the problems on which it is based are explained with regard to a silicon-based memory.
In general, a DRAM memory is formed from a memory cell configuration whose individual memory cells have a selection transistor and a capacitor connected thereto. A memory cell of a ROM memory consists of only a transistor.
In the beginning, memory cell configurations were based on predominantly planar designs. With the stipulation of a constantly increasing packing density, a proposal has already been made for mask ROM applications (read-only memory) which envisages folding the cell area of the memory by introducing parallel longitudinal trenches and thus reducing the cell area when projected onto the wafer surface by up to 50%. The utilization of the vertical direction in the form of capacitances as trench or stacked capacitor is known in the case of DRAMs.
German patent DE 195 14 834 discloses a read-only memory cell configuration having first memory cells with a vertical MOS transistor and second memory cells without a vertical MOS transistor. The memory cells are arranged along opposite sidewalls of mutually parallel strip-type insulation trenches. If the width and spacing of the insulation trenches are chosen to be identical, then the minimum space requirement per memory cell is theoretically 2F.sup.2, where F is the minimum structure size of the manufacturing technology.
German published patent application DE 195 10 042 discloses a read-only memory cell configuration in which the memory cells are arranged in parallel rows. Longitudinal trenches run essentially parallel to the rows. In this case, the rows are respectively arranged alternately on the main area between neighboring longitudinal trenches and on the bottom of the longitudinal trenches. Insulation structures are provided for mutual insulation of the memory cells, which each comprise a MOS transistor. Word lines run transversely with respect to the rows and are each connected to the gate electrodes of MOS transistors arranged along different rows. In this case, the minimum space requirement per memory cell is theoretically 4F.sup.2, where F is the minimum structure size of the respective technology.
The commonly assigned, copending application No. 08/755,456, which corresponds to the German published patent application DE 195 43 539, discloses a RAM memory cell configuration having a vertical storage capacitor with a ferroelectric or paraelectric storage dielectric. In order to fabricate the storage capacitor, a dielectric layer for the storage dielectric is produced in a large-area manner. The dielectric layer is subsequently structured, and first and second electrodes are formed for the storage capacitors.
The storage dielectric used in accordance with the disclosure of the copending application is ferroelectric material for nonvolatile memories, since that material has spontaneous polarization which is present even in the absence of an external electric field. Paraelectric material, on the other hand, is used in DRAM applications, in which a refresh cycle is provided.
In practice, however, the known designs for memory cells comprising a selection transistor and a storage capacitance (for example DRAM) at present only enable cell sizes for a memory cell of 9.6 F.sup.2. The aim is a cell size of 8 F.sup.2 starting with the 1 Gb generation, where F=0.18 .mu.m.